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?2005 silicon storage technology, inc. s71160-13-000 10/06 1 the sst logo and superflash are registered trademarks of silicon storage technology, inc. ssf is a trademark of silicon storage technology, inc. these specifications are subject to change without notice. data sheet 2 mbit / 4 mbit (x8) small-sector flash sst29SF020 / sst29sf040 sst29vf020 / sst29vf040 features: ? organized as 256k x8 / 512k x8 ? single voltage read and write operations ? 4.5-5.5v for sst29SF020/040 ? 2.7-3.6v for sst29vf020/040 ? superior reliability ? endurance: 100,000 cycles (typical) ? greater than 100 years data retention ? low power consumption: ? active current: 10 ma (typical) ? standby current: 30 a (typical) for sst29SF020/040 1 a (typical) for sst29vf020/040 ? sector-erase capability ? uniform 128 byte sectors ? fast read access time: ? 55 ns for sst29SF020/040 ? 70 ns for sst29vf020/040 ? latched address and data ? fast erase and byte-program: ? sector-erase time: 18 ms (typical) ? chip-erase time: 70 ms (typical) ? byte-program time: 14 s (typical) ? chip rewrite time: 4 seconds (typical) for sst29sf/vf020 8 seconds (typical) for sst29sf/vf040 ? automatic write timing ? internal v pp generation ? end-of-write detection ? toggle bit ? data# polling ? ttl i/o compatibility for sst29SF020/040 ? cmos i/o compatibility for sst29vf020/040 ? jedec standard ? flash eeprom pinouts and command sets ? packages available ? 32-lead plcc ? 32-lead tsop (8mm x 14mm) ? all non-pb (lead-free) devices are rohs compliant product description the sst29SF020/040 and sst29vf020/040 are 256k x8 / 512k x8 cmos small-sector flash (ssf) manufac- tured with sst?s proprietary, high-performance cmos superflash technology. the split-gate cell design and thick-oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. the sst29SF020/040 devices write (program or erase) with a 4.5-5.5v power supply. the sst29vf020/040 devices write (program or erase) with a 2.7-3.6v power supply. these devices conf orm to jedec standard pin assignments for x8 memories. featuring high performance byte-program, the sst29SF020/040 and sst29vf020/040 devices pro- vide a maximum byte-program ti me of 20 sec. to protect against inadvertent write, they have on-chip hardware and software data protection schemes. designed, manufac- tured, and tested for a wide spectrum of applications, these devices are offered with a guaranteed endurance of at least 10,000 cycles. data retention is rated at greater than 100 years. the sst29SF020/040 and sst29vf020/040 devices are suited for applications that require convenient and eco- nomical updating of program, configuration, or data mem- ory. for all system applications, they significantly improve performance and reliability, while lowering power consump- tion. they inherently use less energy during erase and program than alternative flash technologies. the total energy consumed is a function of the applied voltage, cur- rent, and time of application. since for any given voltage range, the superflash technology uses less current to pro- gram and has a shorter erase time, the total energy con- sumed during any erase or program operation is less than alternative flash technologies. they also improve flexibility while lowering the cost for program, data, and configuration storage applications. the superflash technology provides fixed erase and pro- gram times independent of the number of erase/program cycles that have occurred. therefore, the system software or hardware does not have to be modified or de-rated as is necessary with alternative flash technologies, whose erase and program times increase with accumulated erase/pro- gram cycles. to meet high density, surface mount requirements, the sst29SF020/040 and sst29vf020/040 devices are offered in 32-lead plcc and 32-lead tsop packages. the pin assignments are shown in figures 2 and 3. sst29sf/vf020 / 0402mb / 4mb (x8) byte-program, small-sector flash memories
2 data sheet 2 mbit / 4 mbit small-sector flash sst29SF020 / sst29sf040 sst29vf020 / sst29vf040 ?2005 silicon storage technology, inc. s71160-13-000 10/06 device operation commands are used to initiate the memory operation func- tions of the device. commands are written to the device using standard microprocessor write sequences. a com- mand is written by asserting we# low while keeping ce# low. the address bus is latc hed on the falling edge of we# or ce#, whichever occurs last. the data bus is latched on the rising edge of we# or ce#, whichever occurs first. read the read operation of the sst29SF020/040 and sst29vf020/040 devices are controlled by ce# and oe#, both have to be low for the system to obtain data from the outputs. ce# is used for device selection. when ce# is high, the chip is deselected and only standby power is con- sumed. oe# is the output control and is used to gate data from the output pins. the data bus is in high impedance state when either ce# or oe# is high. refer to the read cycle timing diagram in figure 4 for further details. byte-program operation the sst29SF020/040 and sst29vf020/040 devices are programmed on a byte-by-byte basis. before program- ming, the sector where the byte exists must be fully erased. the program operation is accomplished in three steps. the first step is the three-byte load sequence for software data protection. the second step is to load byte address and byte data. during the byte-program operation, the addresses are latched on the falling edge of either ce# or we#, whichever occurs last. the data is latched on the ris- ing edge of either ce# or we#, whichever occurs first. the third step is the internal program operation which is initi- ated after the rising edge of the fourth we# or ce#, which- ever occurs first. the program operation, once initiated, will be completed, within 20 s. see figures 5 and 6 for we# and ce# controlled program operation timing diagrams and figure 16 for flowcharts. during the program opera- tion, the only valid reads are data# polling and toggle bit. during the internal program operation, the host is free to perform additional tasks. any commands written during the internal program operation will be ignored. sector-erase operation the sector-erase operation allows the system to erase the device on a sector-by-sector basis. the sst29SF020/ 040 and sst29vf020/040 offer sector-erase mode. the sector architecture is based on uniform sector size of 128 bytes. the sector-erase operation is initiated by executing a six-byte command sequence with sector-erase com- mand (20h) and sector address (sa) in the last bus cycle. the sector address is latc hed on the falling edge of the sixth we# pulse, while the command (20h) is latched on the rising edge of the sixth we# pulse. the internal erase operation begins after the sixth we# pulse. the end-of- erase operation can be determined using either data# polling or toggle bit methods. for timing waveforms, see figure 9. any commands issued during the sector-erase operation are ignored. chip-erase operation the sst29SF020/040 and sst29vf020/040 devices provide a chip-erase operation, which allows the user to erase the entire memory array to the ?1s? state. this is use- ful when the entire device must be quickly erased. the chip-erase operation is initiated by executing a six- byte software data protection command sequence with chip-erase command (10h) with address 555h in the last byte sequence. the internal erase operation begins with the rising edge of the sixth we# or ce#, whichever occurs first. during the internal erase operation, the only valid read is toggle bit or data# polling. see table 4 for the command sequence, figure 10 for the timing diagram, and figure 19 for the flowchart. any commands written during the chip- erase operation will be ignored. write operation status detection the sst29SF020/040 and sst29vf020/040 devices provide two software means to detect the completion of a write (program or erase) cycle, in order to optimize the system write cycle time. the software detection includes two status bits: data# polling (dq 7 ) and toggle bit (dq 6 ). the end-of-write detection mode is enabled after the ris- ing edge of we# which initiates the internal program or erase operation. the actual completion of the nonvolatile write is asyn- chronous with the system; theref ore, either a data# poll- ing or toggle bit read may be simultaneous with the completion of the write cycle. if this occurs, the system may possibly get an erroneous result, i.e., valid data may appear to conflict with either dq 7 or dq 6 . in order to pre- vent spurious rejection, if an erroneous result occurs, the software routine should include a loop to read the accessed location an additional two (2) times. if both reads are valid, then the device has completed the write cycle, otherwise the rejection is valid.
data sheet 2 mbit / 4 mbit small-sector flash sst29SF020 / sst29sf040 sst29vf020 / sst29vf040 3 ?2005 silicon storage technology, inc. s71160-13-000 10/06 data# polling (dq 7 ) when the sst29SF020/040 and sst29vf020/040 devices are in the internal program operation, any attempt to read dq 7 will produce the complement of the true data. once the program operation is completed, dq 7 will produce true data. note that even though dq 7 may have valid data immediately following the completion of an internal write operation, the remaining data outputs may still be invalid: valid data on the entire data bus will appear in subsequent successive read cycles after an interval of 1 s. during internal erase operation, any attempt to read dq 7 will produce a ?0?. once the internal erase operation is completed, dq 7 will produce a ?1?. the data# polling is valid after the rising edge of fourth we# (or ce#) pulse for program operation. for sector- or chip-erase, the data# polling is valid after the rising edge of sixth we# (or ce#) pulse. see figure 7 for data# polling timing diagram and figure 17 for a flow- chart. toggle bit (dq 6 ) during the internal program or erase operation, any con- secutive attempts to read dq 6 will produce alternating ?0?s and ?1?s, i.e., toggling between 0 and 1. when the internal program or erase operation is completed, the toggling will stop. the device is then ready for the next operation. the toggle bit is valid after the rising edge of fourth we# (or ce#) pulse for program operation. for sector or chip- erase, the toggle bit is valid after the rising edge of sixth we# (or ce#) pulse. see figure 8 for toggle bit timing dia- gram and figure 17 for a flowchart. data protection the sst29SF020/040 and sst29vf020/040 devices provide both hardware and software features to protect nonvolatile data from inadvertent writes. hardware data protection noise/glitch protection: a we# or ce# pulse of less than 5 ns will not initiate a write cycle. v dd power up/down detection: the write operation is inhibited when v dd is less than 2.5v for sst29SF020/ 040. the write operation is inhibited when v dd is less than 1.5v. for sst29vf020/040. write inhibit mode: forcing oe# low, ce# high, or we# high will inhibit the write oper ation. this prevents inadvert- ent writes during power-up or power-down. software data protection (sdp) the sst29SF020/040 and sst29vf020/040 provide the jedec approved software data protection scheme for all data alteration operations, i.e., program and erase. any program operation requires the inclusion of a series of three- byte sequence. the three-byte load sequence is used to initiate the program operation, providing optimal protection from inadvertent write operations, e.g., during the system power-up or power-down. any erase operation requires the inclusion of a si x-byte load sequence. these devices are shipped with the software data protection per- manently enabled. the specific software command codes are shown in table 4. during sdp command sequence, invalid commands will abort the device to read mode, within t rc.
4 data sheet 2 mbit / 4 mbit small-sector flash sst29SF020 / sst29sf040 sst29vf020 / sst29vf040 ?2005 silicon storage technology, inc. s71160-13-000 10/06 product identification the product identification mode identifies the devices as sst29SF020, sst29sf040 and sst29vf020, sst29vf040 and manufacturer as sst. this mode may be accessed by software operations. users may use the software product identification operation to identify the part (i.e., using the device id) when using multiple manufactur- ers in the same socket. for details, see table 4 for software operation, figure 11 for the software id entry and read timing diagram, and figure 18 for the software id entry command sequence flowchart. product identificatio n mode exit/reset in order to return to the standard read mode, the software product identification mode must be exited. exit is accom- plished by issuing the software id exit command sequence, which returns the device to the read operation. please note that the software id exit command is ignored during an internal program or erase operation. see table 4 for software command codes, figure 12 for timing wave- form, and figure 18 for a flowchart. figure 1: functional block diagram table 1: product identification address data manufacturer?s id 0000h bfh device id sst29SF020 0001h 24h sst29vf020 0001h 25h sst29sf040 0001h 13h sst29vf040 0001h 14h t1.3 1160 y-decoder i/o buffers and data latches 1160 b1.0 address buffers & latches x-decoder dq 7 - dq 0 memory address oe# ce# we# superflash memory control logic
data sheet 2 mbit / 4 mbit small-sector flash sst29SF020 / sst29sf040 sst29vf020 / sst29vf040 5 ?2005 silicon storage technology, inc. s71160-13-000 10/06 figure 2: pin assignments for 32-lead plcc figure 3: pin assignments for 32-lead tsop (8mm x 14mm) 5 6 7 8 9 10 11 12 13 29 28 27 26 25 24 23 22 21 a7 a6 a5 a4 a3 a2 a1 a0 dq0 a7 a6 a5 a4 a3 a2 a1 a0 dq0 a14 a13 a8 a9 a11 oe# a10 ce# dq7 a14 a13 a8 a9 a11 oe# a10 ce# dq7 4 3 2 1 32 31 30 a12 a15 a16 nc v dd we# a17 a12 a15 a16 a18 v dd we# a17 32-lead plcc top view 1160 32-plcc nh p1.2 14 15 16 17 18 19 20 dq1 dq2 v ss dq3 dq4 dq5 dq6 dq1 dq2 v ss dq3 dq4 dq5 dq6 sst29sf/vf020 sst29sf/vf040 sst29sf/vf020 sst29sf/vf040 sst29sf/vf020 sst29sf/vf040 sst29sf/vf020 sst29sf/vf040 a11 a9 a8 a13 a14 a17 we# v dd nc a16 a15 a12 a7 a6 a5 a4 a11 a9 a8 a13 a14 a17 we# v dd a18 a16 a15 a12 a7 a6 a5 a4 sst29sf/vf020 sst29sf/vf040 sst29sf/vf020 sst29sf/vf040 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 oe# a10 ce# dq7 dq6 dq5 dq4 dq3 v ss dq2 dq1 dq0 a0 a1 a2 a3 oe# a10 ce# dq7 dq6 dq5 dq4 dq3 v ss dq2 dq1 dq0 a0 a1 a2 a3 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1160 32-tsop wh p2.2 standard pinout top view die up
6 data sheet 2 mbit / 4 mbit small-sector flash sst29SF020 / sst29sf040 sst29vf020 / sst29vf040 ?2005 silicon storage technology, inc. s71160-13-000 10/06 table 2: pin description symbol pin name functions a ms 1 -a 0 1. a ms = most significant address a ms = a 17 for sst29sf/vf020 and a 18 for sst29sf/vf040 address inputs to provide memory addresses. during sector-erase a ms -a 8 address lines will select the sector. dq 7 -dq 0 data input/output to ou tput data during read cycles and receive input data during write cycles. data is internally latched during a write cycle. the outputs are in tri-state when oe# or ce# is high. ce# chip enable to activate the device when ce# is low. oe# output enable to gate the data output buffers. we# write enable to control the write operations. v dd power supply to provide power supply voltage: 4.5-5.5v for sst29SF020/040 2.7-3.6v for sst29vf020/040 v ss ground nc no connection pin not connected internally t2.5 1160 table 3: operation modes selection mode ce# oe# we# dq address read v il v il v ih d out a in program v il v ih v il d in a in erase v il v ih v il x 1 1. x can be v il or v ih , but no other value. sector address, xxh for chip-erase standby v ih x x high z x write inhibit x v il x high z/ d out x xxv ih high z/ d out x product identification software mode v il v il v ih see table 4 t3.4 1160
data sheet 2 mbit / 4 mbit small-sector flash sst29SF020 / sst29sf040 sst29vf020 / sst29vf040 7 ?2005 silicon storage technology, inc. s71160-13-000 10/06 table 4: software command sequence command sequence 1st bus write cycle 2nd bus write cycle 3rd bus write cycle 4th bus write cycle 5th bus write cycle 6th bus write cycle addr 1 data addr 1 data addr 1 data addr 1 data addr 1 data addr 1 data byte-program 555h aah 2aah 55h 555h a0h ba 2 data sector-erase 555h aah 2aah 55h 555h 80h 555h aah 2aah 55h sa x 3 20h chip-erase 555h aah 2aah 55h 555h 80h 555h aah 2aah 55h 555h 10h software id entry 4,5 555h aah 2aah 55h 555h 90h software id exit 6 xxh f0h software id exit 6 555h aah 2aah 55h 555h f0h t4.7 1160 1. address format a 14 -a 0 (hex), addresses a 15 -a ms can be v il or v ih , but no other value, for the command sequence for sst29sf/vf020/040. a ms = most significant address a ms = a 17 for sst29sf/vf020 and a 18 for sst29sf/vf040. 2. ba = program byte address 3. sa x for sector-erase; uses a ms -a 7 address lines for sst29sf/vf020/040 4. the device does not remain in software product id mode if powered down. 5. with a ms -a 1 = 0; sst manufacturer?s id = bfh, is read with a 0 = 0, sst29SF020 device id = 24h, is read with a 0 = 1 sst29vf020 device id = 25h, is read with a 0 = 1 sst29sf040 device id = 13h, is read with a 0 = 1 sst29vf040 device id = 14h, is read with a 0 = 1 6. both software id exit operations are equivalent
8 data sheet 2 mbit / 4 mbit small-sector flash sst29SF020 / sst29sf040 sst29vf020 / sst29vf040 ?2005 silicon storage technology, inc. s71160-13-000 10/06 absolute maximum stress ratings (applied conditions greater than t hose listed under ?absolute maximum stress ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these conditions or conditions greater t han those defined in the operational sections of this data sheet is not implied. exposu re to absolute maximum stress rating co nditions may affect device reliability.) temperature under bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55c to +125c storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65c to +150c d. c. voltage on any pin to ground potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0. 5v to v dd +0.5v transient voltage (<20 ns) on any pin to ground potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.0v to v dd +2.0v voltage on a 9 pin to ground potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to 13.2v package power dissipation capability (t a = 25c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0w through hole lead soldering temperature (10 seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300c surface mount solder reflow temperature 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260c for 10 seconds output short circuit current 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 ma 1. excluding certain with-pb 32-plcc units, all packages are 260 c capable in both non-pb and with-pb solder versions. certain with-pb 32-plcc package types are capable of 240 c for 10 seconds; please consult the factory for the latest information. 2. outputs shorted for no more than one second. no more than one output shorted at a time. operating range for sst29SF020/040 range ambient temp v dd commercial 0c to +70c 4.5-5.5v industrial -40c to +85c 4.5-5.5v operating range for sst29vf020/040 range ambient temp v dd commercial 0c to +70c 2.7-3.6v industrial -40c to +85c 2.7-3.6v ac conditions of test input rise/fall time . . . . . . . . . . . . . . 5 ns output load . . . . . . . . . . . . . . . . . . . . . c l = 30 pf for 55 ns output load . . . . . . . . . . . . . . . . . . . . . c l = 100 pf for 70 ns see figures 13, 14, and 15 table 5: dc operating characteristics v dd = 4.5-5.5v for sst29SF020/040 symbol parameter limits test conditions min max units i dd power supply current address input=v il /v ih , at f=1/t rc min v dd =v dd max read 25 ma ce#=oe#=v il , we#=v ih , all i/os open write 30 ma ce#=we#=v il , oe#=v ih i sb1 standby v dd current (ttl input) 3 ma ce#=v ih , v dd =v dd max i sb2 standby v dd current (cmos input) 100 a ce#=v ihc , v dd =v dd max i li input leakage current 1 a v in =gnd to v dd , v dd =v dd max i lo output leakage current 10 a v out =gnd to v dd , v dd =v dd max v il input low voltage 0.8 v v dd =v dd min v ih input high voltage 2.0 v v dd =v dd max v ihc input high voltage (cmos) v dd -0.3 v v dd =v dd max v ol output low voltage 0.4 v i ol =2.1 a, v dd =v dd min v oh output high voltage 2.4 v i oh =-400 a, v dd =v dd min t5.7 1160
data sheet 2 mbit / 4 mbit small-sector flash sst29SF020 / sst29sf040 sst29vf020 / sst29vf040 9 ?2005 silicon storage technology, inc. s71160-13-000 10/06 table 6: dc operating characteristics v dd = 2.7-3.6v for sst29vf020/040 symbol parameter limits test conditions min max units i dd power supply current address input=v il /v ih , at f=1/t rc min v dd =v dd max read 25 ma ce#=oe#=v il , we#=v ih , all i/os open write 30 ma ce#=we#=v il , oe#=v ih i sb standby v dd current 15 a ce#=v ihc , v dd =v dd max i li input leakage current 1 a v in =gnd to v dd , v dd =v dd max i lo output leakage current 10 a v out =gnd to v dd , v dd =v dd max v il input low voltage 0.8 v v dd =v dd min v ih input high voltage 0.7v dd vv dd =v dd max v ihc input high voltage (cmos) v dd -0.3 v v dd =v dd max v ol output low voltage 0.2 v i ol =100 a, v dd =v dd min v oh output high voltage v dd -0.2 v i oh =-100 a, v dd =v dd min t6.9 1160 table 7: recommended system power-up timings symbol parameter minimum units t pu-read 1 1. this parameter is measured only for init ial qualification and after a design or proc ess change that could affect this paramet er. power-up to read operation 100 s t pu-write 1 power-up to program/erase operation 100 s t7.1 1160 table 8: capacitance (t a = 25c, f=1 mhz, other pins open) parameter description test condition maximum c i/o 1 1. this parameter is measured only for init ial qualification and after a design or proc ess change that could affect this paramet er. i/o pin capacitance v i/o = 0v 12 pf c in 1 input capacitance v in = 0v 6 pf t8.1 1160 table 9: reliability characteristics symbol parameter minimum specification units test method n end 1 1. this parameter is measured only for init ial qualification and after a design or proc ess change that could affect this paramet er. endurance 10,000 cycles jedec standard a117 t dr 1 data retention 100 years jedec standard a103 i lt h 1 latch up 100 + i dd ma jedec standard 78 t9.2 1160
10 data sheet 2 mbit / 4 mbit small-sector flash sst29SF020 / sst29sf040 sst29vf020 / sst29vf040 ?2005 silicon storage technology, inc. s71160-13-000 10/06 ac characteristics table 10: read cycle timing parameters v dd = 4.5-5.5v for sst29SF020/040 and 2.7-3.6v for sst29vf020/040 symbol parameter sst29SF020/040 -55 sst29vf020/040 -70 units min max min max t rc read cycle time 55 70 ns t ce chip enable access time 55 70 ns t aa address access time 55 70 ns t oe output enable access time 30 35 ns t clz 1 1. this parameter is measured only for init ial qualification and after a design or proc ess change that could affect this paramet er. ce# low to active output 0 0 ns t olz 1 oe# low to active output 0 0 ns t chz 1 ce# high to high-z output 20 25 ns t ohz 1 oe# high to high-z output 20 25 ns t oh 1 output hold from address change 00ns t10.10 1160 table 11: program/erase cycle timing parameters v dd = 4.5-5.5v for sst29SF020/040 and 2.7-3.6v for sst29vf020/040 symbol parameter min max units t bp byte-program time 20 s t as address setup time 0 ns t ah address hold time 30 ns t cs we# and ce# setup time 0 ns t ch we# and ce# hold time 0 ns t oes oe# high setup time 0 ns t oeh oe# high hold time 10 ns t cp ce# pulse width 40 ns t wp we# pulse width 40 ns t wph 1 1. this parameter is measured only for init ial qualification and after a design or proc ess change that could affect this paramet er. we# pulse width high 30 ns t cph 1 ce# pulse width high 30 ns t ds data setup time 40 ns t dh 1 data hold time 0 ns t ida 1 software id access and exit time 150 ns t se sector-erase 25 ms t sce chip-erase 100 ms t11.9 1160
data sheet 2 mbit / 4 mbit small-sector flash sst29SF020 / sst29sf040 sst29vf020 / sst29vf040 11 ?2005 silicon storage technology, inc. s71160-13-000 10/06 figure 4: read cycle timing diagram figure 5: we# controlled program cycle timing diagram 1160 f03.1 address a ms-0 dq 7-0 we# oe# ce# t ce t rc t aa t oe t olz v ih high-z t clz t oh t chz high-z data valid data valid t ohz note: a ms = most significant address a ms = a 17 for sst29sf/vf020 and a 18 for sst29sf/vf040 1160 f04.1 address a ms-0 dq 7-0 t dh t wph t ds t wp t ah t as t ch t cs ce# sw0 sw1 sw2 555 2aa 555 addr aa 55 a0 data byte (addr/data) oe# we# t bp internal program operation starts note: a ms = most significant address a ms = a 17 for sst29sf/vf020 and a 18 for sst29sf/vf040
12 data sheet 2 mbit / 4 mbit small-sector flash sst29SF020 / sst29sf040 sst29vf020 / sst29vf040 ?2005 silicon storage technology, inc. s71160-13-000 10/06 figure 6: ce# c ontrolled p rogram c ycle t iming d iagram figure 7: data# polling timing diagram 1160 f05.1 address a ms-0 dq 7-0 t dh t cph t ds t cp t ah t as t ch t cs we# sw0 sw1 sw2 555 2aa 555 addr aa 55 a0 data internal program operation starts byte (addr/data) oe# ce# t bp note: a ms = most significant address a ms = a 17 for sst29sf/vf020 and a 18 for sst29sf/vf040 1160 f06.1 address a ms-0 dq 7 dd# d# d we# oe# ce# t oeh t oe t ce t oes
data sheet 2 mbit / 4 mbit small-sector flash sst29SF020 / sst29sf040 sst29vf020 / sst29vf040 13 ?2005 silicon storage technology, inc. s71160-13-000 10/06 figure 8: t oggle b it t iming d iagram figure 9: we# controlled sector-erase timing diagram 1160 f07.1 address a ms-0 dq 6 we# oe# ce# t oe t oeh t ce t oes two read cycles with same outputs note: a ms = most significant address a ms = a 17 for sst29sf/vf020 and a 18 for sst29sf/vf040 1160 f08.1 address a ms-0 dq 7-0 we# sw0 sw1 sw2 sw3 sw4 sw5 555 2aa 2aa 555 555 55 20 55 aa 80 aa sa x oe# ce# six-byte code for sector-erase t se t wp note: this device also supports ce# controlled sector-erase operation the we# and ce# signals are interchangeable as long as minimum timings are met. (see table 11) a ms = most significant address a ms = a 17 for sst29sf/vf020 and a 18 for sst29sf/vf040 sa x = sector address.
14 data sheet 2 mbit / 4 mbit small-sector flash sst29SF020 / sst29sf040 sst29vf020 / sst29vf040 ?2005 silicon storage technology, inc. s71160-13-000 10/06 figure 10: we# c ontrolled c hip -e rase t iming d iagram figure 11: software id entry and read 1160 f09.1 address a ms-0 dq 7-0 we# sw0 sw1 sw2 sw3 sw4 sw5 555 2aa 2aa 555 555 55 10 55 aa 80 aa 555 oe# ce# six-byte code for chip-erase t sce t wp note: this device also supports ce# controlled chip-erase operation the we# and ce# signals are interchangeable as long as minimum timings are met. (see table 11) a ms = most significant address a ms = a 17 for sst29sf/vf020 and a 18 for sst29sf/vf040 1160 f10.1 address a 14-0 dq 7-0 we# sw1 sw0 sw2 device id 555 2aa 555 0000 0001 oe# ce# three-byte sequence for software id entry t wp t wph t aa bf 55 aa 90 t ida note: device id = 24h for sst29SF020, 13h for sst29sf040 25h for sst29vf020, 14h for sst29vf040
data sheet 2 mbit / 4 mbit small-sector flash sst29SF020 / sst29sf040 sst29vf020 / sst29vf040 15 ?2005 silicon storage technology, inc. s71160-13-000 10/06 figure 12: s oftware id e xit and r eset 1160 f11.1 address a 14-0 dq 7-0 t ida t wp t whp we# sw0 sw1 sw2 555 2aa 555 three-byte sequence for sofware id exit and reset oe# ce# aa 55 f0
16 data sheet 2 mbit / 4 mbit small-sector flash sst29SF020 / sst29sf040 sst29vf020 / sst29vf040 ?2005 silicon storage technology, inc. s71160-13-000 10/06 figure 13: ac input/output reference waveforms for sst29SF020/040 figure 14: ac input/output reference waveforms for sst29vf020/040 figure 15: test load examples 1160 f12.0 reference points output input v it v iht v ilt v ot ac test inputs are driven at v iht (3.0v) for a logic ?1? and v ilt (0v) for a logic ?0?. measurement reference points for inputs and outputs are v it (1.5 v dd ) and v ot (1.5 v dd ). input rise and fall times (10% ? 90%) are <10 ns. note: v it - v input te s t v ot - v output te s t v iht - v input high test v ilt - v input low test 1160 f12.0 reference points output input v it v iht v ilt v ot ac test inputs are driven at v iht (0.9 v dd ) for a logic ?1? and v ilt (0.1 v dd ) for a logic ?0?. measurement reference points for inputs and outputs are v it (0.5 v dd ) and v ot (0.5 v dd ). input rise and fall times (10% ? 90%) are <5 ns. note: v it - v input te s t v ot - v output te s t v iht - v input high test v ilt - v input low test 1160 f14a.0 sst29sf040 to tester to dut c l r l low r l high v dd 1160 f14b.0 to tester to dut c l sst29vf040
data sheet 2 mbit / 4 mbit small-sector flash sst29SF020 / sst29sf040 sst29vf020 / sst29vf040 17 ?2005 silicon storage technology, inc. s71160-13-000 10/06 figure 16: byte-program algorithm 1160 f15.0 start load data: aah address: 555h load data: 55h address: 2aah load data: a0h address: 555h load byte address/byte data wait for end of program (t bp , data# polling bit, or toggle bit operation) program completed
18 data sheet 2 mbit / 4 mbit small-sector flash sst29SF020 / sst29sf040 sst29vf020 / sst29vf040 ?2005 silicon storage technology, inc. s71160-13-000 10/06 figure 17: wait options 1160 f16.0 wait t bp , t sce, or t se byte- program/erase initiated internal timer toggle bit ye s ye s no no program/erase completed does dq 6 match? read same byte data# polling program/erase completed program/erase completed read byte is dq 7 = true data? read dq 7 byte- program/erase initiated byte- program/erase initiated
data sheet 2 mbit / 4 mbit small-sector flash sst29SF020 / sst29sf040 sst29vf020 / sst29vf040 19 ?2005 silicon storage technology, inc. s71160-13-000 10/06 figure 18: software id command flowcharts 1160 f17.0 load data: aah address: 555h software id entry command sequence load data: 55h address: 2aah load data: 90h address: 555h wait t ida read software id load data: aah address: 555h software id exit & reset command sequence load data: 55h address: 2aah load data: f0h address: 555h load data: f0h address: xxh return to normal operation wait t ida wait t ida return to normal operation
20 data sheet 2 mbit / 4 mbit small-sector flash sst29SF020 / sst29sf040 sst29vf020 / sst29vf040 ?2005 silicon storage technology, inc. s71160-13-000 10/06 figure 19: erase command sequence 1160 f18.0 load data: aah address: 555h chip-erase command sequence load data: 55h address: 2aah load data: 80h address: 555h load data: 55h address: 2aah load data: 10h address: 555h load data: aah address: 555h wait t sce chip erased to ffh load data: aah address: 555h sector-erase command sequence load data: 55h address: 2aah load data: 80h address: 555h load data: 55h address: 2aah load data: 20h address: sa x load data: aah address: 555h wait t se sector erased to ffh
data sheet 2 mbit / 4 mbit small-sector flash sst29SF020 / sst29sf040 sst29vf020 / sst29vf040 21 ?2005 silicon storage technology, inc. s71160-13-000 10/06 product ordering information device speed suffix1 suffix2 sst29x f xxx - xxx -x x -x x x environmental attribute e 1 = non-pb package modifier h = 32 leads package type n = plcc w = tsop (type 1, die up, 8mm x 14mm) temperature range c = commercial = 0c to +70c i = industrial = -40c to +85c minimum endurance 4 = 10,000 cycles read access speed 55 = 55 ns 70 = 70 ns device density 040 = 4 mbit 020 = 2 mbit function f = chip- or sector-erase byte-program voltag e s = 4.5-5.5v v = 2.7-3.6v 1. environmental suffix ?e? denotes non-pb solder. sst non-pb solder devices are ?rohs compliant?.
22 data sheet 2 mbit / 4 mbit small-sector flash sst29SF020 / sst29sf040 sst29vf020 / sst29vf040 ?2005 silicon storage technology, inc. s71160-13-000 10/06 valid combinations for sst29SF020 sst29SF020-55-4c-nhe sst29SF020-55-4c-whe sst29SF020-55-4i-nhe sst29SF020-55-4i-whe valid combinations for sst29vf020 sst29vf020-70-4c-nhe sst29vf020-70-4c-whe sst29vf020-70-4i-nhe sst29vf020-70-4i-whe valid combinations for sst29sf040 sst29sf040-55-4c-nh sst29sf040-55-4c-wh sst29sf040-55-4c-nhe sst29sf040-55-4c-whe sst29sf040-55-4i-nh sst29sf040-55-4i-wh sst29sf040-55-4i-nhe sst29sf040-55-4i-whe valid combinations for sst29vf040 sst29vf040-70-4c-nh sst29vf040-70-4c-wh sst29vf040-70-4c-nhe sst29vf040-70-4c-whe sst29vf040-70-4i-nh sst29vf040-70-4i-wh sst29vf040-70-4i-nhe sst29vf040-70-4i-whe note: valid combinations are those products in mass producti on or will be in mass production. consult your sst sales representative to confirm availability of valid combinat ions and to determine availability of new combinations.
data sheet 2 mbit / 4 mbit small-sector flash sst29SF020 / sst29sf040 sst29vf020 / sst29vf040 23 ?2005 silicon storage technology, inc. s71160-13-000 10/06 packaging diagrams 32-lead plastic lead chip carrier (plcc) sst package code: nh .040 .030 .021 .013 .530 .490 .095 .075 .140 .125 .032 .026 .032 .026 .029 .023 .453 .447 .553 .547 .595 .585 .495 .485 .112 .106 .042 .048 .048 .042 .015 min. top view side view bottom view 1 232 .400 bsc 32-plcc-nh-3 note: 1. complies with jedec publication 95 ms-016 ae dimensions, although some dimensions may be more stringent. 2. all linear dimensions are in inches (max/min). 3. dimensions do not include mold flash. maximum allowable mold flash is .008 inches. 4. coplanarity: 4 mils. .050 bsc .050 bsc optional pin #1 identifier .020 r. max. r. x 30
24 data sheet 2 mbit / 4 mbit small-sector flash sst29SF020 / sst29sf040 sst29vf020 / sst29vf040 ?2005 silicon storage technology, inc. s71160-13-000 10/06 32-lead thin small outline package (tsop) 8mm x 14mm sst package code: wh 32-tsop-wh-7 note: 1. complies with jedec publication 95 mo-142 ba dimensions, although some dimensions may be more stringent. 2. all linear dimensions are in millimeters (max/min). 3. coplanarity: 0.1 mm 4. maximum allowable mold flash is 0.15 mm at the package ends, and 0.25 mm between leads. 1.20 max. 1mm pin # 1 identifier 12.50 12.30 14.20 13.80 0.70 0.50 8.10 7.90 0.27 0.17 0. 50 bsc 1.05 0.95 0.15 0.05 0.70 0.50 0- 5 detail
data sheet 2 mbit / 4 mbit small-sector flash sst29SF020 / sst29sf040 sst29vf020 / sst29vf040 25 ?2005 silicon storage technology, inc. s71160-13-000 10/06 table 12: revision history number description date 05 ? 2002 data book may 2002 06 ? removed 512 kbit, 1 mbit, and 2 mbit parts ? commercial temperature and 70 ns parts removed ? ph package is no longer offered ? part number changes - see page 22 for additional information ? changes to tables 5 and 6 on page 8 and page 9: ? clarified test conditions for power supply current and read parameters ? clarified i dd write to be program and erase ? corrected i dd program and erase from 20 ma to 30 ma ? corrected i dd read from 20 ma to 25 ma ? clarified measurement reference points v it and v ot to be 1.5v instead of 1.5v dd ? corrected the v ol test condition i ol to be 2.1 ma instead of 2.1 a in table 5 on page 8 mar 2003 07 ? corrected the test conditions for the read parameter in table 5 on page 8 apr 2003 08 ? added commercial temperatures for all packages (see page 22 for details) aug 2003 09 ? 2004 data book ? changed status to ?data sheet? dec 2003 10 ? added 70 ns technical data and mpns for sst29vf040 only feb 2004 11 ? added rohs compliance information on page 1 and in the ?product ordering information? on page 21 ? reinstated 512 kbit, 1 mbit, and 2 mbit devices and mpns (excluding the pdip package) ? removed 55 ns technical data and mpns for sst29vf040 ? added non-pb mpns for all devices ? clarified the solder temperature profile under ?absolute maximum stress ratings? on page 8 mar 2005 12 ? removed all entries related to sst29sf/vf512 and sst29sf/vf010 ? removed leaded parts for 020 products. nov 2005 13 ? changed idd read from 20ma to 25ma, and changed idd write from 20ma to 30ma in table 5 on page 8 and table 6 on page 9 oct 2006 silicon storage technology, inc. ? 1171 sonora court ? sunnyvale, ca 94086 ? telephone 408-735-9110 ? fax 408-735-9036 www.superflash.com or www.sst.com

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